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First, the basic concept of vias

Via is one of the important components of multilayer PCB, and the cost of drilling usually accounts for 30% to 40% of PCB manufacturing cost. Simply put, every hole on the PCB can be called a via. From the point of view of function, vias can be divided into two categories: one is used for electrical connection between layers; the other is used for fixing or positioning devices. In terms of process, these vias are generally divided into three categories, namely, blind vias, buried vias and through vias. Blind vias are located on the top and bottom surfaces of the printed circuit board and have a certain depth. They are used to connect the surface line and the underlying inner line. The depth of the hole usually does not exceed a certain ratio (aperture). Buried hole refers to the connection hole located in the inner layer of the printed circuit board, which does not extend to the surface of the circuit board. The above-mentioned two types of holes are located in the inner layer of the circuit board, and are completed by a through-hole forming process before lamination, and several inner layers may be overlapped during the formation of the via. The third type is called a through hole, which penetrates the entire circuit board and can be used for internal interconnection or as a component mounting positioning hole. Because the through hole is easier to implement in the process and the cost is lower, most of the printed circuit boards use it instead of the other two kinds of through holes. The via holes mentioned below, unless otherwise specified, are considered as via holes.

From a design point of view, a via is mainly composed of two parts, one is the drill hole in the middle, and the other is the pad area around the drill hole. The size of these two parts determines the size of the via. Obviously, in high-speed, high-density PCB design, designers always hope that the smaller the via hole is, the better, so that more wiring space can be left on the board. In addition, the smaller the via hole, the parasitic capacitance of its own. The smaller it is, the more suitable it is for high-speed circuits. However, the reduction of hole size also brings about an increase in cost, and the size of vias cannot be reduced indefinitely. It is limited by process technologies such as drilling and plating: the smaller the hole, the more drilling The longer the hole takes, the easier it is to deviate from the center position; and when the depth of the hole exceeds 6 times the diameter of the drilled hole, it cannot be guaranteed that the hole wall can be uniformly plated with copper. For example, if the thickness (through hole depth) of a normal 6-layer PCB board is 50Mil, then under normal conditions, the minimum drilling diameter provided by the PCB manufacturer can only reach 8Mil. With the development of laser drilling technology, the size of the hole can be smaller and smaller. Generally, a via with a diameter less than or equal to 6Mils is called a microhole. Microvias are often used in HDI (High Density Interconnect Structure) design. Microvia technology allows vias to be directly punched on the pad (Via-in-pad), which greatly improves circuit performance and saves wiring space.

Vias appear as breakpoints with discontinuous impedance on the transmission line, which will cause signal reflections. Generally, the equivalent impedance of a via is about 12% lower than that of a transmission line. For example, the impedance of a 50 ohm transmission line will decrease by 6 ohms when passing through the via (specifically, it is related to the size and thickness of the via, not an absolute reduction). However, the reflection caused by the discontinuous impedance of the via is actually very small, and its reflection coefficient is only: (44-50)/(44+50)=0.06. The problems caused by the via are more concentrated on parasitic capacitance and inductance. Impact.

Second, the parasitic capacitance and inductance of the via

The via itself has parasitic stray capacitance. If it is known that the diameter of the solder mask on the ground layer of the via is D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric constant of the board substrate Is ε, the parasitic capacitance of the via is approximately: C=1.41εTD1/(D2-D1)

The main effect of the parasitic capacitance of the via hole on the circuit is to extend the rise time of the signal and reduce the speed of the circuit. For example, for a PCB board with a thickness of 50Mil, if the diameter of the via pad is 20Mil (the diameter of the hole is 10Mils), and the diameter of the solder mask is 40Mil, then we can approximate the size of the via using the above formula The parasitic capacitance is roughly:

C=1.41x4.4x0.050x0.020/(0.040-0.020)=0.31pF

The rise time change caused by this part of the capacitance is roughly:

T10-90=2.2C(Z0/2)=2.2x0.31x(50/2)=17.05ps

It can be seen from these values that although the effect of the rise delay caused by the parasitic capacitance of a single via is not very obvious, if the via is used multiple times in the trace to switch between layers, multiple vias will be used , The design must be carefully considered. In actual design, the parasitic capacitance can be reduced by increasing the distance between the via hole and the copper area (Anti-pad) or reducing the diameter of the pad.

Parasitic capacitances exist in vias as well as parasitic inductances. In the design of high-speed digital circuits, the harm caused by the parasitic inductances of vias is often greater than the impact of parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor and weaken the filtering effect of the entire power system. We can use the following empirical formula to simply calculate the parasitic inductance of a via:

L=5.08h[ln(4h/d)+1]

Where L refers to the inductance of the via, h is the length of the via, and d is the diameter of the center hole. It can be seen from the formula that the diameter of the via has a small influence on the inductance, and the length of the via has the greatest influence on the inductance. Still using the above example, the inductance of the via can be calculated as:

L=5.08x0.050[ln(4x0.050/0.010)+1]=1.015nH

If the rise time of the signal is 1ns, then its equivalent impedance is: XL=πL/T10-90=3.19Ω. Such impedance can no longer be ignored when high-frequency current passes. Special attention should be paid to the fact that the bypass capacitor needs to pass through two vias when connecting the power layer and the ground layer, so that the parasitic inductance of the via will double.

Third, how to use vias

Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to circuit design. In order to reduce the adverse effects caused by the parasitic effects of the vias, the following can be done in the design:

1. Considering both cost and signal quality, select a reasonable size via size. If necessary, you can consider using different sizes of vias. For example, for power or ground vias, you can consider using a larger size to reduce impedance, and for signal traces, you can use smaller vias. Of course, as the size of the via decreases, the corresponding cost will increase.

2. The two formulas discussed above can be concluded that using a thinner PCB is beneficial to reduce the two parasitic parameters of the via.

3. Try not to change the layers of the signal traces on the PCB board, that is, try not to use unnecessary vias.

4. The pins of the power supply and the ground should be drilled nearby, and the lead between the via and the pin should be as short as possible. Consider playing multiple vias in parallel to reduce the equivalent inductance.

5. Place some grounded vias near the vias of the signal layer to provide the closest return to the signal. You can even place some redundant ground vias on the PCB.

6. For high-speed PCB boards with higher density, you can consider using micro vias.